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PRELIMINARY DATA SHEET
256MB DDR SDRAM S.O.DIMM
HB54A2568KN-A75B/B75B/10B (32M words x 64 bits, 2 Banks)
Description
The HB54A2568KN is Double Data Rate (DDR) SDRAM Module, mounted 256M bits DDR SDRAM (HM5425161BTT) sealed in TSOP package, and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD). The HB54A2568KN is organized as 16M x 64 x 2 bank mounted 8 pieces of 256M bits DDR SDRAM. Read and write operations are performed at the cross points of the CK and the /CK. This high-speed data transfer is realized by the 2 bits prefetch-pipelined architecture. Data strobe (DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. An outline of the products is 200-pin socket type package (dual lead out). Therefore, it makes high density mounting possible without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board.
Features
* 200-pin socket type package (dual lead out) Outline: 67.6mm (Length) x 31.75mm (Height) x 3.80mm (Thickness) Lead pitch: 0.6mm * 2.5V power supply (VCC) * SSTL-2 interface for all inputs and outputs * Clock frequency: 133 MHz (max) (-A75B/B75B) : 100 MHz (max) (-10B) * Data inputs, outputs and DM are synchronized with DQS * 4 banks can operate simultaneously and independently (Component) * Burst read/write operation * Programmable burst length: 2, 4, 8 Burst read stop capability * Programmable burst sequence Sequential Interleave * Start addressing capability Even and Odd * Programmable /CAS latency (CL): 2, 2.5 * 8192 refresh cycles: 7.8s (8192row /64ms) * 2 variations of refresh Auto refresh Self refresh
Document No. E0148H20 (Ver. 2.0) Date Published April 2002 (K) Japan URL: http://www.elpida.com Elpida Memory, Inc. 2001-2002 Hitachi, Ltd. 2001 Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
HB54A2568KN-A75B/B75B/10B
Ordering Information
Part number HB54A2568KN-A75B*1 HB54A2568KN-B75B*2 HB54A2568KN-10B*3 Clock frequency MHz (max.) 133 MHz 133 MHz 100 MHz /CAS latency 2.0 2.5 2.0 Package Contact pad
200-pin dual lead out socket Gold type
Notes: 1. 143 MHz operation at /CAS latency = 2.5. 2. 100 MHz operation at /CAS latency = 2.0. 3. 125 MHz operation at /CAS latency = 2.5.
Pin Configurations
Front side 1 pin 39 pin 41 pin 199 pin
2 pin
40 pin 42 pin Back side
200 pin
Pin No. 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
Pin name VREF VSS DQ0 DQ1 VCC DQS0 DQ2 VSS DQ3 DQ8 VCC DQ9 DQS1 VSS DQ10 DQ11 VCC CK0 /CK0 VSS DQ16 DQ17 VCC DQS2 DQ18
Pin No. 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99
Pin name VSS DQ19 DQ24 VCC DQ25 DQS3 VSS DQ26 DQ27 VCC NC NC VSS NC NC VCC NC NC VSS CK2 /CK2 VCC CKE1 NC A12
Pin No. 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
Pin name VREF VSS DQ4 DQ5 VCC DM0 DQ6 VSS DQ7 DQ12 VCC DQ13 DM1 VSS DQ14 DQ15 VCC VCC VSS VSS DQ20 DQ21 VCC DM2 DQ22
Pin No. 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100
Pin name VSS DQ23 DQ28 VCC DQ29 DM3 VSS DQ30 DQ31 VCC NC NC VSS NC NC VCC NC NC VSS VSS VCC VCC CKE0 NC A11
Preliminary Data Sheet E0148H20 (Ver. 2.0)
2
HB54A2568KN-A75B/B75B/10B
Pin No. 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 Pin name A9 VSS A7 A5 A3 A1 VCC A10/AP BA0 /WE /S0 NC VSS DQ32 DQ33 VCC DQS4 DQ34 VSS DQ35 DQ40 VCC DQ41 DQS5 VSS Pin No. 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Pin name DQ42 DQ43 VCC VCC VSS VSS DQ48 DQ49 VCC DQS6 DQ50 VSS DQ51 DQ56 VCC DQ57 DQS7 VSS DQ58 DQ59 VCC SDA SCL VCCSPD VCCID Pin No. 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 Pin name A8 VSS A6 A4 A2 A0 VCC BA1 /RAS /CAS /S1 NC VSS DQ36 DQ37 VCC DM4 DQ38 VSS DQ39 DQ44 VCC DQ45 DM5 VSS Pin No. 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Pin name DQ46 DQ47 VCC /CK1 CK1 VSS DQ52 DQ53 VCC DM6 DQ54 VSS DQ55 DQ60 VCC DQ61 DM7 VSS DQ62 DQ63 VCC SA0 SA1 SA2 NC
Preliminary Data Sheet E0148H20 (Ver. 2.0)
3
HB54A2568KN-A75B/B75B/10B
Pin Description
Pin name A0 to A12 BA0, BA1 DQ0 to DQ63 /RAS /CAS /WE /S0, /S1 CKE0, CKE1 CK0 to CK2 /CK0 to /CK2 DQS0 to DQS7 DM0 to DM7 SCL SDA SA0 to SA2 VCC VCCSPD VREF VSS VCCID NC Function Address input Row address Column address Data input/output Row address strobe command Column address strobe command Write enable Chip select Clock enable Clock input Differential clock input Input and output data strobe Input mask Clock input for serial PD Data input/output for serial PD Serial address input Power for internal circuit Power for serial EEPROM Input reference voltage Ground VCC identification flag No connection A0 to A12 A0 to A8
Bank select address
Preliminary Data Sheet E0148H20 (Ver. 2.0)
4
HB54A2568KN-A75B/B75B/10B
Serial PD Matrix*
Byte No. 0 1 2 3 4 5 6 7 8 9
1
Function described Number of bytes utilized by module manufacturer Total number of bytes in serial PD device Memory type Number of row address Number of column address Number of DIMM banks Module data width Module data width continuation DDR SDRAM cycle time, CL = X -A75B -B75B -10B SDRAM access from clock (tAC) -A75B/B75B -10B DIMM configuration type Refresh rate/type Primary SDRAM width Error checking SDRAM width SDRAM device attributes: Minimum clock delay back-to-back column access SDRAM device attributes: Burst length supported SDRAM device attributes: Number of banks on SDRAM device SDRAM device attributes: /CAS latency SDRAM device attributes: /CS latency SDRAM device attributes: /WE latency SDRAM module attributes SDRAM device attributes: General Minimum clock cycle time at CLX - 0.5 -A75B -B75B/10B
Bit7 1 0 0 0 0 0 0 0
Bit6 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1
Bit5 Bit4 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1
Bit3 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0
Bit2 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 0
Bit1 Bit0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0
Hex value 80 08 07 0D 09 02 40 00 04 70 75 80 70 80 00 82 10 00 01 0E 04 0C 01 02 20 80 75 A0 70 80 00 00 50
Comments 128 256 byte SDRAM DDR 13 9 2 64 bits 0 (+) SSTL 2.5V CL = 2.5*5
Voltage interface level of this assembly 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1
10
0.7ns*5 0.8ns*5 Non-parity 7.8 s Self refresh x 16 Not used 1 CLK 2, 4, 8 4 2, 2.5 0 1 Unbuffered 0.2V CL = 2*5
11 12 13 14 15 16 17 18 19 20 21 22 23
24
Maximum data access time (tAC) from 0 clock at CLX - 0.5 -A75B/B75B -10B 1 Minimum clock cycle time at 0 CLX - 1 Maximum data access time (tAC) from 0 clock at CLX - 1 Minimum row precharge time (tRP) 0
0.7ns*5 0.8ns*5
25 26 27
20ns
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Byte No. 28 29 30 Function described Minimum row active to row active delay (tRRD) Minimum /RAS to /CAS delay (tRCD) Minimum active to precharge time (tRAS) -A75B/B75B -10B 31 Module bank density Address and command setup time before clock (tIS) -A75B/B75B -10B 33 Bit7 0 0 0 0 0 Bit6 0 1 0 0 0 Bit5 Bit4 1 0 1 1 1 1 1 0 1 0 Bit3 1 0 1 0 0 Bit2 1 0 1 0 0 Bit1 Bit0 0 0 0 1 0 0 0 1 0 0 Hex value 3C 50 2D 32 20 Comments 15ns 20ns 45ns 50ns 1 bank/ 2 bank 128 MB 1.1ns*5 1.2ns*5 1.1ns*5 1.2ns*5 0.5ns*5 0.6ns*5 0.5ns*5 0.6ns*5 Future use 65ns*5 70ns*5 75ns*5 80ns*5 15ns*5 500ps*5 600ps*5 750ps*5 1000ps*5 Future use Initial
32
1 1
0 1 0 1 1 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0
1 0 1 0 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0
1 0 1 0 1 0 1 0 0 0 0 0 1 1 1 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0
0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0
0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 0
B0 C0 B0 C0 50 60 50 60 00 41 46 4B 50 3C 32 3C 75 A0 00 00
Address and command hold time after clock (tIH) 1 -A75B/B75B -10B 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Data input setup time before clock (tDS) -A75B/B75B -10B Data input hold time after clock (tDH) -A75B/B75B -10B Superset information Active command period (tRC) -A75B/B75B -10B Auto refresh to active/ Auto refresh command cycle (tRFC) -A75B/B75B -10B SDRAM tCK cycle max. (tCK max.) Dout to DQS skew -A75B/B75B -10B Data hold skew (tQHS) -A75B/B75B -10B Superset information SPD revision
34
35
36 to 40 41
42
43 44
45
46 to 61 62
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Byte No. 63
Function described Checksum for bytes 0 to 62 -A75B -B75B -10B
Bit7 1 1 0 0 0 x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x x *
3
Bit6 0 1 1 0 0 x 1 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 1 1 0 0 0 0 x x
Bit5 Bit4 0 0 1 0 0 x 0 0 1 1 0 1 1 1 1 0 0 1 0 0 1 1 1 1 0 0 1 1 1 1 x x 1 0 1 0 0 x 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 x x
Bit3 1 1 1 0 0 x 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 x x
Bit2 1 1 0 1 0 x 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 x x
Bit1 Bit0 0 0 1 1 0 x 0 1 0 0 0 1 0 1 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 x x 0 0 1 1 0 x 0 0 1 0 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 0 0 0 0 0 x x
Hex value 9C CC 7B 07 00 xx 48 42 35 34 41 32 35 36 38 4B 4E 2D 41 42 31 37 30 35 42 42 20 20 30 20 xx xx
Comments 156 204 123 HITACHI *2 (ASCII-8bit code) H B 5 4 A 2 5 6 8 K N -- A B 1 7 0 5 B B (Space) (Space) Initial (Space) Year code (BCD) Week code (BCD)
64 65 to 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85
Manufacturer's JEDEC ID code Manufacturer's JEDEC ID code Manufacturing location Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number Module part number -A75B -B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number -A75B/B75B -10B Module part number Revision code Revision code Manufacturing date Manufacturing date Module serial number Manufacturer specific data
86
87
88
89 to 90 91 92 93 94 95 to 98 99 to 127
*4
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" These SPD are based on JEDEC Committee Ballot JC-42.5-99-129. 2. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows "J" on ASCII code.) 3. Bytes 95 through 98 are assembly serial number. 4. All bits of 99 through 127 are not defined ("1" or "0"). 5. These specifications are defined based on component specification, not module.
Preliminary Data Sheet E0148H20 (Ver. 2.0)
8
HB54A2568KN-A75B/B75B/10B
Block Diagram
/S1 /S0 RS DQS0 RS DM0 8 DQ0 to DQ7 RS DQS1 RS DM1 8 DQ8 to DQ15 RS I/O8 to I/O15 I/O8 to I/O15 DQ40 to DQ47 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ32 to DQ39 RS DQS5 RS DM5 8 RS I/O8 to I/O15 RS DQS6 RS LDM 8 DQ16 to DQ23 RS DQS3 RS DM3 8 DQ24 to DQ31 RS I/O8 to I/O15 I/O8 to I/O15 DQ56 to DQ63 RS I/O0 to I/O7 UDQS UDM I/O0 to I/O7 UDQS UDM DQ48 to DQ55 RS DQS7 RS DM7 8 RS I/O8 to I/O15 I/O8 to I/O15 UDM UDM UDQS LDM DM6 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDM LDM LDQS I/O8 to I/O15 UDM UDM UDQS LDM LDM DM4 8 RS I/O0 to I/O7 I/O0 to I/O7 UDQS LDQS RS DQS4 RS LDM LDM LDQS
/S
LDQS
/S
/S
LDQS
/S
D0
D4
D2
D6
RS DQS2 RS DM2 LDQS
/S
LDQS
/S
/S
LDQS
/S
D1
D5
D3
D7
* D0 to D7 : 256M bits DDR SDRAM U0 : 2k bits EEPROM Rs : 22 BA0 to BA1 A0 to AN /RAS /CAS /WE CKE0 CKE1 VCCSPD VREF VCC Serial PD SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D7) SDRAMs (D0 to D3) SDRAMs (D4 to D7) SPD SDRAMs (D0 to D7) SDRAMs (D0 to D7), VCC and VCCQ CK0 /CK0 CK1 /CK1 CK2 10 pF VSS VCCID Open SDRAMs (D0 to D7), SPD /CK2 Notes : 1. DQ wiring may differ from that described in this drawing; however DQ/DM/DQS relationships are maintained as shown. VCCID strap connections: (for memory device VCC, VCCQ) Strap out (open): VCC = VCCQ Strap in (closed): VCC VCCQ 2. The SDA pull-up registor is reguired due to the open-drain/open-collector output. 3. The SCL pull-up registor is recommended, because of the normal SCL lime inactive "high" state. 4 loads 4 loads SCL SA0 SA1 SA2 SCL A0 A1 A2 SDA SDA
U0 WP
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Logical Clock Net Structure
4DRAM loads DRAM1
120 DIMM connector
DRAM2
DRAM3
DRAM4
Preliminary Data Sheet E0148H20 (Ver. 2.0)
10
HB54A2568KN-A75B/B75B/10B
Pin Functions (1)
CK (CLK), /CK (/CLK) (input pin): The CK and the /CK are the master clock inputs. All inputs except DMs, DQSs and DQs are referred to the cross point of the CK rising edge and the VREF level. When a read operation, DQSs and DQs are referred to the cross point of the CK and the /CK. When a write operation, DMs and DQs are referred to the cross point of the DQS and the VREF level. DQSs for write operation are referred to the cross point of the CK and the /CK. /S (/CS) (input pin): When /S is Low, commands and data can be input. When /S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. /RAS, /CAS, and /WE (input pins): These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins): Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the VREF level in a bank active command cycle. Column address (AY0 to AY8) is loaded via the A0 to the A8 at the cross point of the CK rising edge and the VREF level in a read or a write command cycle. This column address becomes the starting address of a burst operation. A10 (AP) (input pin): A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1, BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. BA0, BA1 (input pin): BA0/BA1 are bank select signals. The memory array is divided into bank 0, bank 1, bank 2 and bank 3. If BA1 = Low and BA0 = Low, bank 0 is selected. If BA1 = High and BA0 = Low, bank 1 is selected. If BA1 = Low and BA0 = High, bank 2 is selected. If BA1 = High and BA0 = High, bank 3 is selected. CKE (input pin): CKE controls power down and self-refresh. The power down and the self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. The CKE level must be kept for 1 CK cycle (= LCKEPW) at least, that is, if CKE changes at the cross point of the CK rising edge and the VREF level with proper setup time tIS, at the next CK rising edge CKE level must be kept with proper hold time tIH.
Pin Functions (2)
DQ (input and output pins): Data are input to and output from these pins. DQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes (as input). DM (input pins): DM is the reference signal of the data input mask function. DMs are sampled at the cross point of DQS and VREF VCC and VCCQ (power supply pins): 2.5V is applied. (VCC is for the internal circuit and VCCQ is for the output buffer.) VCCSPD (power supply pin): 2.5V is applied (For serial EEPROM). VSS (power supply pin): Ground is connected.
Detailed Operation Part, AC Characteristics and Timing Waveforms
Refer to the HM5425161B/HM5425801B/HM5425401B Series datasheet (E0086H).
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Electrical Specifications
Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC, VCCQ IOUT PT Topr Tstg Value -1.0 to +4.6 -1.0 to +4.6 50 8 0 to +65 -50 to +100 Unit V V mA W C C Note 1 1
Notes: 1. Respect to VSS. DC Operating Conditions (TA = 0 to +65C)
Parameter Supply voltage Symbol VCC, VCCQ VSS Input reference voltage Termination voltage DC Input high voltage DC Input low voltage DC Input signal voltage DC differential input voltage VREF VTT VIH VIL VIN (dc) min. 2.3 0 1.15 VREF - 0.04 VREF + 0.18 -0.3 -0.3 Typ 2.5 0 1.25 VREF -- -- -- -- max. 2.7 0 1.35 VREF + 0.04 VCCQ + 0.3 VREF - 0.18 VCCQ + 0.3 VCCQ + 0.6 Unit V V V V V V V V 1 1 1, 3 1, 4 5 6 Notes 1, 2
VSWING (dc) 0.36
Notes: 1. 2. 3. 4. 5. 6.
All parameters are referred to VSS, when measured. VCCQ must be lower than or equal to VCC. VIH is allowed to exceed VCC up to 4.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to -1.0V for the period shorter than or equal to 5ns. VIN (dc) specifies the allowable dc execution of each differential input. VSWING (dc) specifies the input differential voltage required for switching.
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
DC Characteristics 1 (TA = 0 to 65C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Operating current (ACTV-PRE) Symbol ICC0 Grade -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B -A75B -B75B -10B max. 600 560 480 820 760 680 144 120 96 320 280 240 200 160 120 400 360 320 1220 1160 1100 1160 1100 1040 1020 980 880 24 Unit mA Test condition CKE VIH, tRC = min. CKE VIH, BL = 2, CL = 2.5, tRC = min. CKE VIL Notes 1, 2, 5
Operating current (ACTV-READ-PRE)
ICC1
mA
1, 2, 5
Idle power down standby current
ICC2P
mA
4
Idle standby current
ICC2N
mA
CKE VIH, /CS VIH
4
Active power down standby current
ICC3P
mA
CKE VIL CKE VIH, /CS VIH tRAS = max. CKE VIH, BL = 2, CL = 2.5 CKE VIH, BL = 2, CL = 2.5 tRFC = min., Input VIL or VIH Input VCC - 0.2V Input 0.2V.
3
Active standby current Operating current (Burst read operation) Operating current (Burst write operation) Auto refresh current Self refresh current
ICC3N
mA
3
ICC4R
mA
1, 2, 5, 6
ICC4W
mA
1, 2, 5, 6
ICC5 ICC6
mA mA
Notes. 1. 2. 3. 4. 5. 6. 7.
These ICC data are measured under condition that DQ pins are not connected. One bank operation. One bank active. All banks idle. Command/Address transition once per one cycle. Data/Data mask transition twice per one cycle. The ICC data on this table are measured with regard to tCK = min. in general.
DC Characteristics 2 (TA = 0 to 65C, VCC, VCCQ = 2.5V 0.2V, VSS = 0V)
Parameter Input leakage current Output leakage current Output high voltage Output low voltage Symbol ILI ILO VOH VOL min. -10 -10 VTT + 0.76 -- max. 10 10 -- VTT - 0.76 Unit A A V V Test condition VCC VIN VSS VCC VOUT VSS IOH (max.) = -15.2mA IOL (min.) = 15.2mA Notes
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Pin Capacitance (TA = 25C, VCC, VCCQ = 2.5V 0.2V)
[Parameter Input capacitance Input capacitance Data and DQS input/output capacitance Symbol CI1 CI2 CO Pins Address, /RAS, /CAS, /WE CKE, /S CK, /CK DQ, DQS, DM min. max. 60 40 27 Unit pF pF pF Notes 1 1 1, 2
Notes: 1.These parameters are measured on conditions: f = 100MHz, VOUT = VCCQ/2, VOUT = 0.2V. 2. Dout circuits are disabled. Timing Parameter Measured in Clock Cycle for Unbuffered DIMM
Number of clock cycle Parameter Write to pre-charge command delay (same bank) Read to pre-charge command delay (same bank) Write to read command delay (to input all data) Burst stop command to write command delay (CL = 2) (CL = 2.5) Burst stop command to DQ High-Z (CL = 2) (CL = 2.5) Read command to write command delay (to output all data) (CL = 2) (CL = 2.5) Pre-charge command to High-Z (CL = 2) (CL = 2.5) Write command to data in latency Write recovery DM to data in latency Register set command to active or register set command Self refresh exit to non-read command Self refresh exit to read command Power down entry Power down exit to command input CKE minimum pulse width Symbol tWPD tRPD tWRD tBSTW tBSTW tBSTZ tBSTZ tRWD tRWD tHZP tHZP tWCD tWR tDMD tMRD tSNR tSRD tPDEN tPDEX tCKEPW min. 3 + BL/2 BL/2 2 + BL/2 2 3 2 2.5 2 + BL/2 3 + BL/2 2 2.5 1 2 0 2 10 200 1 1 1 max.
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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HB54A2568KN-A75B/B75B/10B
Physical Outline
Unit: mm 67.60 63.60 11.55 18.45 3.80 (DATUM -A-)
4x Full R
Component area (Front)
20.0 4.00
31.75 6.00
2.15
11.40 4.20
A
47.40
B 2.45 1.00 0.10
4.20 1.50 2.45
2
199
1
11.40
47.40
200
2.15 R0.50 0.20
R0.50 0.20
2x 1.80
Component area (Back)
4.00 0.10
(DATUM -A-)
2.00 Min.
Detail A
(DATUM -A-) FULL R
4.00 0.10
Detail B
0.60 1.80 1.00 0.10 0.45 0.03
ECA-TS2-0019-01
Preliminary Data Sheet E0148H20 (Ver. 2.0)
15
0.25 Max
2.55
HB54A2568KN-A75B/B75B/10B
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
MDE0202
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function.
CME0107
Preliminary Data Sheet E0148H20 (Ver. 2.0)
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